1. Field of the Invention
The present invention relates to a CODEC and, more particularly, to a CODEC having a DSP which can perform a plurality of algorithm processes.
2. Description of the Related Art
In recent years, with the development of communication networks, a CODEC (coder and decoder) having a larger capacity has been required.
Conventionally, a CODEC has a DSP (digital signal processor) therein so as to encode and decode a digital signal by the DSP.
FIG. 1 is a block diagram of a conventional mask-type DSP. The DSP 200 shown in FIG. 1 comprises a ROM 201, a RAM 202, an IO port 203 and a DSP core 204. The ROM 201 stores programs for operations of the DSP 200. The RAM 202 stores working data. Data is input from or output to an external device via the IO port 203. The DSP core 204 executes programs loaded from the ROM 201 by using the work data received from the RAM 202. The DSP core 204 has a program counter (PC) 205 which serves as an access pointer of the ROM 201.
When the DSP 200 is in operation, programs stored in the ROM 201 are sequentially read by the DSP core 204 in an order starting from an address designated by the PC 205, and the read programs are executed by the DSP core 204. A result of execution of the programs is output from the IO port 203. Additionally, when the DSP 200 is in operation, the work data stored in the RAM 202 is read by the DSP core 204, if necessary, and the read work data is processed by the DSP core 204. The processed work data is stored in the RAM 202.
As mentioned above, since the programs and the work data are separately stored in different memories, the DSP can perform a high-speed processing.
FIG. 2 is a block diagram of the DSP 200 shown in FIG. 1 in a state in which a signal having two channels is processed. As shown in FIG. 2, the RAM 202 has tow independent memory areas so as to process the signal having two channels. One of the two memory areas stores work data for a channel (1) and the other stores work data for a channel (2). By structuring the RAM 202 as mentioned above, programs in the ROM 201 are executed twice within a unit time so as to achieve a processing of the signal having the two channels.
The above description is for a case in which an algorithm (programs) of each channel is the same. Conventionally, when a plurality of algorithms are required, a plurality of CODECs each of which processes according to only one specific algorithm are provided. Accordingly, in the conventional system, algorithms to be executed cannot be changed in response to a dynamic change in network traffic.
In order to change algorithms in response to a dynamic change in network traffic, a plurality of algorithms must be stored in a single CODEC. However, a memory provided in a DSP of a conventional CODEC does not have a capacity sufficient for storing programs for executing a plurality of algorithms. Accordingly, when the conventional DSP executes an algorithm different from an algorithm being executed, there is a problem in that an execution of a current program must be temporarily stopped so as to load other programs to the memory in the DSP.